用Verilog实现并串装换

摘要

一、并串转换模块

       并串转换的原理是：先将八位数据暂存于一个四位寄存器器中，然后左移输出到一位输出端口，这里通过load_valid信号指示并行数据输入。

1.1 用移位寄存器实现

module parallel_serial(
  clk, rst_n, load_valid, data_i, ser_data_o
);

input clk, rst_n, en;
input [7:0]    para_data_in;
output         ser_data_o;
 
reg [7:0]  data_buf;

always @(posedge clk or negedge rst_n) begin
	if (rst_n == 1'b0) begin
		ser_data_o <= 1'b0;
		data_buf   <= 8'b0;
	end
	else if (load_valid == 1'b1)
		data_buf <= para_data_in;
	else
		data_buf <= data_buf << 1; 	//将寄存器内的值左移，依次读出
		//data_buf <= {data_buf[6:0],1'b0};
end

assign ser_data_o = data_buf[7];

endmodule

1.2 用计数器实现

module b_c(clk, rst_n, valid, para_data_in, ser_data_out);
input clk, rst_n;
input [3:0] para_data_in;
output reg  valid;
output reg  ser_data_o;
 
reg [3:0]  count;
reg [3:0]  data;

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
       count      <= 0;
       valid      <= 0;;
       data       <= para_data_in;
       ser_data_o <= 0;
    end
    else begin
       if(count < 4) begin
           count         <= count + 1;
           valid         <= 1;
           data          <= {data[2:0], data[3]};
           ser_data_o    <= data[3];
       end
       else begin
           count         <= 0;
           valid         <= 0;
           ser_data_o    <= 0;
       end
    end
end

endmodule