【ARMv8M Cortex-M33 系列 7 -- RA4M2 移植 RT-Thread 问题总结】

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文章目录

- 问题小结
- - 栈未对齐

经过几天的调试，成功将rt-thead 移植到 RA4M2（Cortex-M33 核）上，thread 和 shell 命令已经都成功支持。
在这里插入图片描述

问题小结

在完成 rt-thread 代码 Makefile 编译系统搭建后，就开始着手 rt-thread OS 的移植，不幸的是开始就遇到了问题：cortex-m33/context_gcc.S在退出 PendSV_Handler的时候发生了 HardFault_Handler，由于没有打印信息也不知道是什么原因导致 hardfault，此外由于很久没有调试Cortex-M系列的core了，也不知道去查看哪些寄存器来分析错误原因？

栈未对齐

Memory zones:
  Zone: "Default" Description: Default access mode
Cortex-M33 identified.
J-Link>h
PC = 000002EC, CycleCnt = 003535BF
R0 = 20000C50, R1 = 20001A28, R2 = 00000000, R3 = 00000003
R4 = 00000000, R5 = FFFFFFBC, R6 = 00000000, R7 = 00000000
R8 = DEADBEEF, R9 = DEADBEEF, R10= DEADBEEF, R11= DEADBEEF
R12= 00000002
SP(R13)= 20000C28, MSP= 20000C28, PSP= 20001A28, R14(LR) = FFFFFFFD
XPSR = 2900000E: APSR = nzCvQ, EPSR = 01000000, IPSR = 00E (PendSV)
CFBP = 00000000, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 00
MSPLIM = 20000848
PSPLIM = 00000000

Security extension regs:
MSP_S = 20000C28, MSP_NS = 00000000
MSPLIM_S = 20000848, MSPLIM_NS = 00000000
PSP_S = 20001A28, PSP_NS = 1F36C7B0
PSPLIM_S = 00000000, PSPLIM_NS = 00000000
CONTROL_S  = 00, FAULTMASK_S  = 00, BASEPRI_S  = 00, PRIMASK_S  = 00
CONTROL_NS = 00, FAULTMASK_NS = 00, BASEPRI_NS = 00, PRIMASK_NS = 00

FPS0 = 00000000, FPS1 = 00000000, FPS2 = 00000000, FPS3 = 00000000
FPS4 = 00000000, FPS5 = 00000000, FPS6 = 00000000, FPS7 = 00000000
FPS8 = 00000000, FPS9 = 00000000, FPS10= 00000000, FPS11= 00000000
FPS12= 00000000, FPS13= 00000000, FPS14= 00000000, FPS15= 00000000
FPS16= 00000000, FPS17= 00000000, FPS18= 00000000, FPS19= 00000000
FPS20= 00000000, FPS21= 00000000, FPS22= 00000000, FPS23= 00000000
FPS24= 00000000, FPS25= 00000000, FPS26= 00000000, FPS27= 00000000
FPS28= 00000000, FPS29= 00000000, FPS30= 00000000, FPS31= 00000000
FPSCR= 00000000
J-Link>mem32 0x20001a18 16
20001A18 = DEADBEEF DEADBEEF DEADBEEF DEADBEEF
20001A28 = DEADBEEF DEADBEEF DEADBEEF DEADBEEF
20001A38 = 00000000 00000000 00000000 00000000
20001A48 = 00000000 00000AAD 0000055D 01000000
20001A58 = C9EC9E68 000005A9 1F58CD19 ABFBE429
20001A68 = 1D0D6F06 117A1FBC
J-Link>mem32 0x20001a08 16
20001A08 = 00000000 FFFFFFBC 00000000 00000000
20001A18 = DEADBEEF DEADBEEF DEADBEEF DEADBEEF
20001A28 = DEADBEEF DEADBEEF DEADBEEF DEADBEEF
20001A38 = 00000000 00000000 00000000 00000000
20001A48 = 00000000 00000AAD 0000055D 01000000
20001A58 = C9EC9E68 000005A9
J-Link>

cortex-m33/cpuport.c

rt_uint8_t *rt_hw_stack_init(void       *tentry,
                             void       *parameter,
                             rt_uint8_t *stack_addr,
                             void       *texit)
{
    struct stack_frame *stack_frame;
    rt_uint8_t         *stk;
    unsigned long       i;

    stk  = stack_addr + sizeof(rt_uint32_t);
    stk  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8);
    stk -= sizeof(struct stack_frame);

    stack_frame = (struct stack_frame *)stk;

    /* init all register */
    for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++)
    {
        ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef;
    }

    stack_frame->exception_stack_frame.r0  = (unsigned long)parameter; /* r0 : argument */
    stack_frame->exception_stack_frame.r1  = 0;                        /* r1 */
    stack_frame->exception_stack_frame.r2  = 0;                        /* r2 */
    stack_frame->exception_stack_frame.r3  = 0;                        /* r3 */
    stack_frame->exception_stack_frame.r12 = 0;                        /* r12 */
    stack_frame->exception_stack_frame.lr  = (unsigned long)texit;     /* lr */
    stack_frame->exception_stack_frame.pc  = (unsigned long)tentry;    /* entry point, pc */
    stack_frame->exception_stack_frame.psr = 0x01000000L;              /* PSR */

    stack_frame->tz = 0x00;
    stack_frame->lr = 0xFFFFFFBC;
    stack_frame->psplim = 0x00;
    stack_frame->control = 0x00;

    /* return task's current stack address */
    return stk;

栈结构：

struct exception_stack_frame
{
    rt_uint32_t r0;
    rt_uint32_t r1;
    rt_uint32_t r2;
    rt_uint32_t r3;
    rt_uint32_t r12;
    rt_uint32_t lr;
    rt_uint32_t pc;
    rt_uint32_t psr;
};

struct stack_frame
{
    rt_uint32_t tz;
    rt_uint32_t lr;
    rt_uint32_t psplim;
    rt_uint32_t control;

    /* r4 ~ r11 register */
    rt_uint32_t r4;
    rt_uint32_t r5;
    rt_uint32_t r6;
    rt_uint32_t r7;
    rt_uint32_t r8;
    rt_uint32_t r9;
    rt_uint32_t r10;
    rt_uint32_t r11;

    struct exception_stack_frame exception_stack_frame;
};