verilog HDLBits刷题[Counters]“Count1to10”---Decade counter again
📅 2026/7/23 19:24:39
👁️ 阅读次数
📝 编程学习
一、题目
Make a decade counter that counts 1 through 10, inclusive. The reset input is synchronous, and should reset the counter to 1.
Module Declaration
module top_module ( input clk, input reset, output [3:0] q);
二、分析
同步高有效复位,计数器变为1;否则,计数器从1加到10,然后恢复为1,再加到10
三、代码实现
module top_module ( input clk, input reset, output reg[3:0] q); always@(posedge clk) if(reset) q<=4'd1; else if(q==4'd10) q<=4'd1; else q<=q+4'd1; endmodule 或者 module top_module ( input clk, input reset, output [3:0] q); reg [3:0]cnt; always @(posedge clk)begin if(reset|cnt==4'd10) cnt<=4'd1; else cnt<=cnt+4'd1; end assign q=cnt; endmodule四、时序
编程学习
技术分享
实战经验