8255 boot介绍及bring up经验分享

这篇文章会简单的介绍8255的启动流程，然后着重介绍8255在实际项目中新硬件上的bring up工作，可以给大家做些参考。

8255 boot介绍

下面这些信息来自文档：《QAM8255P IVI Boot and CoreBSP Architecture Technical Overview》 80-42847-11 Rev. AC，如果已经对这个文档比较熟悉可以跳过这个部分。如果没有看过，建议一定要认真看一遍。

1. After the chipset is reset, the SAIL and Qualcomm® Kryo™ CPU Gold core 0 comes out of reset. 
1a. SAIL configures the pre-built-in self-test (pre-BIST) and go into wait for interrupt (WFI) and hardware BIST controller unit (HBCU), which is a 
hardware controller performs the BIST on SAIL. SAIL PBL initializes hardware and loads SAIL hypervisor to run.
1b. SAIL hypervisor loads the SW1/SW2/SW3 images.
1c. APPS core0 executes application primary boot loader (APPS PBL) pre-BIST configuration and goes into WFI and wait for SAIL communication 
to run BIST on APSS. After Phase-1 BIST, SAIL sends post BIST reset to APSS, APSS reset and the Kryo Gold core 0, APPS PBL initializes 
hardware (timer, PRNG, clocks, and so on), enables caches and memory management unit (MMU), and detects the boot device according to 
the boot option configuration:
□ Default boot option for APSS: UFS
□ Default boot option for SAIL: NOR
□ Default boot option: Overridden by EDL cookie or force USB GPIO
2a. APPS PBL loads and authenticates XBL loader (region #1) from the boot device to the Boot IMEM.
2b. APPS PBL loads and authenticates XBL SDI (region #2) from the boot device to on-chip internal memory (OCIMEM).
2c. APPS PBL loads XBL SEC (region #0) from the boot device to boot IMEM. XBL SEC is a QTI-signed ELF segment, which locks xPUs. XBL 
SEC runs the security configuration in the EL3 mode
3. XBL SEC runs the security configuration in the EL3 mode and after it is done, it will inform SAIL hypervisor that APPS is ready for the phase 
BIST-II on DPU, Camera, CamNoc, NSP, Ethernet, PCIe, and so on.
4a. XBL loader will take over control and continue to load multi-image signature and integrity check (MISC).
4b. XBL loader loads and authenticates XBLConfig image.
4c. XBL loader loads SHRM.
4d. XBL loader loads and authenticates MISC image.
4e. XBL loader loads and authenticates the AOP image from the boot device to the AOP CodeRAM.
4f. XBL loader brings the AOP processor out of reset.
4g. XBL loader will then load and authenticate the CPU firmware. 
4h. XBL loader loads and authenticates Qualcomm® Trusted Execution Environment (TEE) into pseudo internal memory (pIMEM).
4i. XBL loader loads and authenticates Qualcomm® Hypervisor Execution Environment (HEE). 
4j. Loads and authenticates XBL core from XBL image.
4k. XBL jumps to XBL_SEC and XBL SEC transfers execution to the Qualcomm TEE.
5. Qualcomm TEE transfers the execution to Qualcomm HEE, Qualcomm HEE runs at EL2 mode. Qualcomm HEE configures SMMUs and 
provides virtualization support.
6. Qualcomm HEE transfers the execution to XBL core(region #3). It runs at nonsecure EL1 mode
7. Linux loader application (part of application boot loader firmware volume (ABL FV)) loads and authenticates the HLOS kernel with verified boot, 
jumps to HLOS. HLOS runs at nonsecure EL1 mode
8-13. HLOS Peripheral image loader (PIL) driver loads all subsystems iris firmware (FW), camera FW, audio FW, sensor FW, turing FW, deep 
learning FW images to DDR and configures the clocks and power rails, if necessary. HLOS PIL driver executes a secure channel manager 
(SCM) call to Qualcomm TEE to request a secure PIL driver, authenticates images, and Qualcomm HEE brings each subsystem out of reset.
QAM8255P Cold Boot Flow – Phase 2 BIST

8255 bring up经验分享

这几天刚刚把新到的8255的硬件完成了bring up，中间遇到了挺多问题，趁着现在还有些印象抓紧记录一下。

8255 boot硬件框架

1，由于功能安全的要求，8255的boot流程和8155有很大的差异

2，MCU和SAIL（安全岛）在boot的流程中需要多次握手，且SAIL软件正常工作时才会放行MD(main domain)域的软件

3，MCU-SAIL之间通信方式为UART，同时SAIL会向外输出ERR_PIN1/PIN2来表明当前的异常状态

4，SAIL和MD之间是通过mailbox进行通信，他们之间也会做一些状态监控

5，这里的MD主域指的是APPS，即application processes，我们常说的A核

6，这里的MCU/VIP型号可能是TC397也可能是瑞萨的RH850系列

8255 bring up前期准备

bring up工作更像是阶段性的总结工作，对这一阶段的工作成果进行验证和总结，打个比喻，你可以认为bring up是一次期中考试。前期工作做的好不好，准备的充不充分，将会在这个时刻得到充分的验证。所以越是前期工作准备的越充分，bring up节点到来的时候，成功bring up的难度就越小，成功率就越高，软硬件的问题也就越少。

硬件设计阶段

在前期的硬件设计阶段，你需要：

1，参与硬件原理图设计的评审会

2，检查review pin mux/HSIS

文档准备

软件需要提前阅读熟悉下面几个文档：

QAM8255P IVI Boot and CoreBSP Architecture Technical Overview

Qualcomm® Snapdragon Ride™ Platform Automotive Reference (SA8775P/SA8650P/SRV1H/SRV1M/SA8255P/ SA8620P/SA7255P) Vehicle Interface Processor (Aurix) User Guide)

SoC-MCU Protocol – Boot and Safety Status Messages