【Verilog】big_small

【Verilog】big_small_cnt

通用大小计数器

`timescale 1ns / 1ps
//
// Company: 
// Engineer:    wengf
// Create Date: 
// Design Name: 
// Module Name: big_small_cnt
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// Dependencies: 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 通用的大小计数器，输入想要开始的条件，直到条件终止
//
module big_small_cnt(
clk       ,
rst       ,
clk_p     ,
start     ,

//BIG_LENGTH,// 添加

big_cnts  ,
small_cnts
    );
//    
parameter BIG_LENGTH=16'd8;
parameter SMALL_LENGTH=8'd11;
//
input clk,rst,clk_p,start;
//input [15:0] BIG_LENGTH;//添加

output [15:0] big_cnts;
output [7:0] small_cnts;
//
reg [7:0] small_cnts;
always @ (posedge clk or posedge rst)//小计数器
begin
	if(rst)
	begin
	small_cnts<=8'hff;
	end
	
	else if(clk_p)
	begin
		if(start)//起始位置
		begin
		small_cnts<=8'd0;	
		end
		
		else if((small_cnts==SMALL_LENGTH-1)&&(big_cnts<BIG_LENGTH-1))//所需长度减1,在这里面进行循环，当big_cnt大于该长度后，自动停止
		begin
		small_cnts<=8'd0;		
		end
		
		else if(big_cnts<=BIG_LENGTH-1)//所需长度减1,在这里面进行循环，当big_cnt大于该长度后，结束循环，保持循环达不到的最大值
		begin
		small_cnts<=small_cnts +1'b1;			
		end
		
		else
		begin
		small_cnts<=small_cnts;		
		end
	end
	
	else
	begin
	small_cnts<=small_cnts;			
	end
end
//
reg [15:0] big_cnts;
always @ (posedge clk or posedge rst)
begin
	if(rst)
	begin
	big_cnts<=16'hffff;
	end
	
	else if((start)&&(clk_p))//起始位置 
	begin
	big_cnts<=16'd0;	
	end
	
	else if((small_cnts==SMALL_LENGTH-1)&&(clk_p))所需长度减1，最大值受最小值控制，按照最小值走几个周期即可。
	begin
	big_cnts<=big_cnts + 1'b1;		
	end
	
	else
	begin
	big_cnts<=big_cnts;			
	end
end
//


endmodule

通用大小计数器，去除 clk_p

`timescale 1ns / 1ps
//
// Company: 
// Engineer:    wengf
// Create Date: 
// Design Name: 
// Module Name: big_small_cnt
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// Dependencies: 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 通用的大小计数器，输入想要开始的条件，直到条件终止
//
module big_small_cnt(
    clk             ,
    rst             ,
    start           ,
    
    forward_cnts    ,
    backward_cnts   , 
    big_cnts        ,
    small_cnts      ,
    small_pulse_start,
    small_pulse_end,
    pulse_end
);
  
parameter BIG_LENGTH=16'd8;
parameter SMALL_LENGTH=8'd8;
parameter COUNT = BIG_LENGTH * SMALL_LENGTH;

input clk,rst,start;
output [15:0] forward_cnts,backward_cnts;
output [15:0] big_cnts;
output [7 :0] small_cnts;
output small_pulse_start;
output small_pulse_end;
output pulse_end;

reg [15:0] forward_cnts,backward_cnts;
reg [15:0] big_cnts;
reg [7:0] small_cnts;
reg small_pulse_start,small_pulse_end,pulse_end;

always @ (posedge clk or posedge rst)//小计数器
begin
	if(rst)
	begin
	forward_cnts<=16'hffff;
	end
	else if(start)//起始位置
	begin
	forward_cnts<=16'd0;	
	end
	
	else if(big_cnts<=BIG_LENGTH-1)//所需长度减1,在这里面进行循环，当big_cnt大于该长度后，结束循环，保持循环达不到的最大值
	begin
	forward_cnts<=forward_cnts +1'b1;			
	end
	
	else
	begin
	forward_cnts<=forward_cnts;		
	end
end

always @ (posedge clk or posedge rst)//小计数器
begin
	if(rst)
	begin
	backward_cnts <= 16'hffff;
	end
	else if(start)//起始位置
	begin
	backward_cnts <= COUNT-1'b1;	
	end
	
	else if(big_cnts<=BIG_LENGTH-1)//所需长度减1,在这里面进行循环，当big_cnt大于该长度后，结束循环，保持循环达不到的最大值
	begin
	backward_cnts<=backward_cnts-1'b1;			
	end
	
	else
	begin
	backward_cnts<=backward_cnts;		
	end
end


always @ (posedge clk or posedge rst)//小计数器
begin
	if(rst)
	begin
	small_cnts<=8'hff;
	end
	else if(start)//起始位置
	begin
	small_cnts<=8'd0;	
	end
	
	else if((small_cnts==SMALL_LENGTH-1)&&(big_cnts<BIG_LENGTH-1))//所需长度减1,在这里面进行循环，当big_cnt大于该长度后，自动停止
	begin
	small_cnts<=8'd0;		
	end
	
	else if(big_cnts<=BIG_LENGTH-1)//所需长度减1,在这里面进行循环，当big_cnt大于该长度后，结束循环，保持循环达不到的最大值
	begin
	small_cnts<=small_cnts +1'b1;			
	end
	
	else
	begin
	small_cnts<=small_cnts;		
	end
end

always @ (posedge clk or posedge rst)//小计数器
begin
	if(rst)
	begin
	small_pulse_start<=1'b0;
	end
	else if(start)//起始位置
	begin
	small_pulse_start<=1'b1;
	end
	
	else if((small_cnts==SMALL_LENGTH-1)&&(big_cnts<BIG_LENGTH-1))//所需长度减1,在这里面进行循环，当big_cnt大于该长度后，自动停止
	begin
	small_pulse_start<=1'b1;	
	end
	
	else
	begin
	small_pulse_start<=1'b0;	
	end
end

always @ (posedge clk or posedge rst)//小计数器
begin
	if(rst)
	begin
	small_pulse_end <= 1'b0;
	end
	else if(start)//起始位置
	begin
	small_pulse_end <= 1'b0;
	end
	
	else if(small_cnts==SMALL_LENGTH-2)//所需长度减1,在这里面进行循环，当big_cnt大于该长度后，自动停止
	begin
	small_pulse_end <=8'd1;		
	end
	
	else
	begin
	small_pulse_end <= 1'b0;
	end
end

always @ (posedge clk or posedge rst)
begin
	if(rst)
	begin
	big_cnts<=16'hffff;
	end
	
	else if(start)//起始位置 
	begin
	big_cnts<=16'd0;	
	end
	
	else if(small_cnts==SMALL_LENGTH-1) 
	begin
	big_cnts<=big_cnts + 1'b1;		
	end
	
	else
	begin
	big_cnts<=big_cnts;			
	end
end

// pulse_end
always @ (posedge clk or posedge rst)
begin
	if(rst)
	begin
	pulse_end<=1'b0;
	end
	
	else if(start)//起始位置 
	begin
	pulse_end <= 1'b0;
	end
	
	else if((small_cnts==SMALL_LENGTH-1) && (big_cnts==BIG_LENGTH-1)) 
	begin
	pulse_end <= 1'b1;
	end
	
	else
	begin
	pulse_end <= 1'b0;
	end
end

endmodule

在这里插入图片描述

wire [15:0] forward_cnts,backward_cnts;
wire [15:0] big_cnts;
wire [7:0] small_cnts;
wire small_pulse_start,small_pulse_end;
wire pulse_end;

big_small_cnt
# ( .BIG_LENGTH(16'd8), 
    .SMALL_LENGTH(16'd3))
big_small_cnt(
    .clk                (clk),
    .rst                (rst),
    .start              (cnts == 8'd10),
    
    .forward_cnts       (forward_cnts),
    .backward_cnts      (backward_cnts),
    .big_cnts           (big_cnts),
    .small_cnts         (small_cnts),
    .small_pulse_start  (small_pulse_start),
    .small_pulse_end    (small_pulse_end),
    .pulse_end          (pulse_end)
);