![verilog HDLBits刷题[Bulid a circuit from a simulation waveform]“Sim/circuit5”---Combinational circuit5](http://pic.xiahunao.cn/yaotu/verilog HDLBits刷题[Bulid a circuit from a simulation waveform]“Sim/circuit5”---Combinational circuit5)
1、题目
2、分析
当c为大于等于4时，q为f；c=0，q=b；c=1，q=e；c=2，q=a；c=3，q=d，相当于多路选择器
3、代码
module top_module ( input [3:0] a, input [3:0] b, input [3:0] c, input [3:0] d, input [3:0] e, output reg [3:0] q ); always @(*) begin case (c) 0 : q <= b; 1 : q <= e; 2 : q <= a; 3 : q <= d; default : q <= 4'hf; endcase end endmodule4、结果