![verilog HDLBits刷题[Verification:Writing Testbenches]“Tb/tb1”---Testbench1](http://pic.xiahunao.cn/yaotu/verilog HDLBits刷题[Verification:Writing Testbenches]“Tb/tb1”---Testbench1)
1、题目
2、分析
写一个testbench，产生如图A和B信号,注意时间的相对性
3、代码
module top_module ( output reg A, output reg B );// // generate input patterns here initial begin A = 1'b0; B = 1'b0; # 10 A = 1'b1; # 5 B = 1'b1; # 5 A = 1'b0; # 20 B = 1'b0; end endmodule4、结果
verilog HDLBits刷题[Verification:Writing Testbenches]“Tb/tb1”---Testbench1