结构级硬件描述

module structual_design ( output y_out, input sel_in, input a_in, input b_in ); logic temp_1 ,tmp_2,tmp_3; and u1(tmp_2, sel_in,a_in); and u2(tmp_3, tmp_1, b_in); not u3(tmp_1,sel_in); or u4(y_out, tmp_2, tmp_3); endmodule

RTL ANALYSIS

SYNTHESIS